Recently, while the operating frequency of CPUs has remarkably increased than before, the increase of operating frequency of memories has gently increased compared with that of CPUs to meet the requirement for greater capacities. The resultant disparity between CPUs and memories in operating frequency is bringing to a problem of no significant improvement in the overall performance of systems.
A prefetch buffer or cache readable with high speed is generally used to solve the problem as follows. Instructions to be necessary in advance are stored in the prefetch buffer or cache, and they are read from that. Accordingly, the delays in reading out of the memory are covered with the function of the prefetch buffer or cache, and devices with the memory are improved.
When the program being executed includes any branch instruction, it is necessary to execute a prefetch that properly anticipates a target (destination) instruction for branch and reads it out to a prefetch buffer or the like.
One of Methods of the prefetch is that anticipates the target address for branch on the basis of history of the execution of the branch instruction and reads the target address anticipated branching destination instruction out of the memory into the prefetch buffer. However, this involves another problem that, where processing is actually branched in accordance with a branch instruction, a configuration in which the aforementioned anticipation is done when the instruction is executed, the series of instructions after the branching cannot be prefetched in time.
In view of this problem, a technique by which the possibility of branch is anticipated at the stage of prefetching instructions and prefetching the subsequent series of instructions is disclosed in Japanese Patent Laid-Open No. H6 (1994)-274341 (hereafter “Patent Reference 1”).